Fangzhou Liu (刘方舟)
Ph.D. Student |
I am currently a second-year Ph.D. student at the Department of Computer Science and Engineering, The Chinese University of Hong Kong (CUHK), under the supervision of Prof. Bei Yu and Prof. Farzan Farnia since Fall 2023. Previously, I received my B.E. in the School of Electronic Science and Engineering from Nanjing Univeristy (NJU) in 2023.
Machine Learning in EDA
Logic Synthesis Optimization
[C2] Fangzhou Liu, Guannan Guo, Yuyang Ye, Ziyi Wang, Wenjie Fu, Weihua Sheng, Bei Yu, “GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays”, ACM International Symposium on Physical Design (ISPD), Austin, Mar. 16–19, 2025.
[C1] Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, Bei Yu, “CBTune: Contextual Bandit Tuning for Logic Synthesis”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Valencia, Spain, Mar. 25–27, 2024. (paper)(slides)(poster)
Ph.D. Computer Science and Engineering, The Chinese University of Hong Kong, Aug 2023 - present
B.Eng. VLSI Design & System Integration, School of Electronic Science and Engineering, Nanjing Univeristy, Sep 2019 - June 2023
Research Intern, Huawei Hong Kong Research Center, Feb 2024 - Sep 2024
Research Intern, Shanghai Artificial Intelligence Laboratory, Sep 2022 - Jun 2023
CENG2010, 2023-R1, Digital Logic Design Laboratory
CSCI1510, 2023-R2, Computer Principles and C Programming
2nd Place Award, ICCAD contest, 2024
Xiakedao EDA2 Challenge Second Prize Winner, ODC computation for clock gating, 2024
“KIRIN Cup” and First Place Award, Integrated Circuit EDA Elite Challenge, 2023
Postgraduate Scholarship, CUHK, 2023-2027